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| HD74AC165 Parallel-Load 8-bit Shift Register REJ03D0254-0200Z (Previous ADE-205-374 (Z)) Rev.2.00 Jul.16.2004 Description This 8-bit serial shift register shifts data from QA to QH when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock. Features * Outputs Source/Sink 24 mA * Ordering Information Part Name HD74AC165FPEL HD74AC165RPEL Package Type SOP-16 pin (JEITA) Package Code Package Abbreviation Taping Abbreviation (Quantity) FP-16DAV FP RP EL (2,000 pcs/reel) EL (2,500 pcs/reel) SOP-16 pin (JEDEC) FP-16DNV Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement SL 1 CP 2 E3 Parallel Inputs F4 G5 H6 QH 7 GND 8 (Top view) 16 VCC Clock 15 Inhibit 14 D 13 C 12 B 11 A 10 SI 9 QH Parallel Inputs Rev.2.00, Jul.16.2004, page 1 of 6 HD74AC165 Logic Symbol 15 11 12 13 14 3 4 5 6 1 2 10 Clock Inhibit SL CP SI A B C DE F GH QH QH 9 7 Pin Names A to H SI CP SL Clock Inhibit QH, QH Parallel Inputs Serial Input Clock Input Shift Load Clock Inhibit Outputs Truth Table Inputs SL L H H H H H: L: X: : X L L L H Clock Inhibit X L CP X X H L X SI Parallel A ****** H a ****** h X X X X a QAD H L QAD Internal Outputs QA QB b QBO QAn QAn QBO h QHO QGn QCn QHO Outputs QH X High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Rev.2.00, Jul.16.2004, page 2 of 6 HD74AC165 Logic Diagram Parallel Inputs A B C D E F G H Preset QA S Clock QA R Clear Preset QB S Clock QB R Clear Preset QC S Clock QC R Clear Preset QD S Clock QD R Clear Preset QE S Clock QE R Clear Preset QF S Clock QF R Clear Preset QG S Clock QG R Clear Preset QH S Clock QH R Clear Output QH Output QH SI SL CP Clock Inhibit Absolute Maximum Ratings Item Supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or ground current per output pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ratings -0.5 to 7 -20 20 -0.5 to Vcc+0.5 -50 50 -0.5 to Vcc+0.5 50 50 -65 to +150 Unit V mA mA V mA mA V mA mA C VI = -0.5V VI = Vcc+0.5V VO = -0.5V VO = Vcc+0.5V Condition Recommended Operating Conditions Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Symbol VCC VI, VO Ta tr, tf 2 to 6 0 to VCC -40 to +85 8 Ratings V V C ns/V VCC = 3.0V VCC = 4.5 V VCC = 5.5 V Unit Condition Rev.2.00, Jul.16.2004, page 3 of 6 HD74AC165 DC Characteristics Item Symbol VIH Vcc (V) 3.0 4.5 5.5 VIL 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 VOL 5.5 3.0 4.5 5.5 3.0 4.5 Input leakage current Dynamic output current* Quiescent supply current IIN IOLD IOHD ICC 5.5 5.5 5.5 5.5 5.5 min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.58 3.94 4.94 -- -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 -- -- -- 0.002 0.001 0.001 -- -- -- -- -- -- -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.32 0.32 0.32 0.1 -- -- 8.0 Ta = -40 to +85C min. max. 2.1 -- 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.48 3.80 4.80 -- -- -- -- -- -- -- 86 -75 -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.37 0.37 0.37 1.0 -- -- 80 A mA mA A V VOUT = 0.1 V or VCC -0.1 V Unit Condition Input Voltage V VOUT = 0.1 V or VCC -0.1 V Output voltage VOH VIN = VIL or VIH IOUT = -50 A VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA VIN = VIL or VIH IOUT = 50 A VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VIN = VCC or GND VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics Ta = +25C CL = 50 pF Min Typ Max 85 100 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -- -- 11.0 8.0 12.0 8.5 13.5 9.5 9.0 6.5 11.5 8.5 10.0 7.5 -- -- 17.5 11.5 18.0 12.5 19.5 13.5 14.0 9.5 20.5 14.0 16.5 11.0 Ta = -40C to +85C CL = 50 pF Min Max 70 90 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -- -- 20.5 13.5 21.5 14.5 22.5 15.5 16.5 11.0 23.5 16.0 19.5 12.5 MHz ns ns ns ns ns ns Item Maximum count frequency Propagation delay CP to QH or QH Propagation delay CP to QH or QH Propagation delay H to QH or QH Propagation delay H to QH or QH Propagation delay SL to QH or QH Propagation delay SL to QH or QH Note: Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Unit 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V Rev.2.00, Jul.16.2004, page 4 of 6 HD74AC165 AC Operating Requirements Ta = +25C CL = 50 pF Item Setup time, HIGH or LOW H to SL Hold time, HIGH or LOW H to SL Setup time, HIGH or LOW Sin to CP Hold time, HIGH or LOW Sin to CP Setup time, HIGH or LOW SL to CP Hold time, HIGH or LOW SL to CP Recovery time clock inhibit to CP Clock pulse width Note: Symbol VCC (V)*1 Typ tsu 3.3 3.5 th tsu th tsu th trec tw 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V 2.5 -1.0 -0.5 1.0 0.5 1.5 1.0 3.0 2.0 -2.0 -1.0 2.5 2.0 3.0 3.0 Ta = -40C to +85C CL = 50 pF Unit ns ns ns ns ns ns ns ns Guaranteed Minimum 5.0 6.0 4.0 0.5 0.5 3.5 3.0 2.0 2.0 5.0 4.0 0.0 0.0 3.5 3.0 5.5 4.5 4.5 0.5 0.5 4.0 3.5 2.0 2.0 6.0 4.5 0.0 0.0 3.5 3.0 7.0 5.0 Capacitance Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 50 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition Rev.2.00, Jul.16.2004, page 5 of 6 HD74AC165 Package Dimensions As of January, 2003 10.06 10.5 Max 16 9 5.5 Unit: mm 1 *0.20 0.05 8 0.80 Max 2.20 Max 0.20 7.80 + 0.30 - 1.15 1.27 0.10 0.10 0 - 8 0.70 0.20 *0.40 0.06 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) FP-16DAV -- Conforms 0.24 g *Ni/Pd/Au plating As of January, 2003 Unit: mm 9.9 10.3 Max 16 9 3.95 1 1.27 0.635 Max 8 0.11 0.14 + 0.04 - 1.75 Max *0.20 0.05 0.10 6.10 + 0.30 - 1.08 0 - 8 + 0.67 0.60 - 0.20 *0.40 0.06 0.15 0.25 M *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g Rev.2.00, Jul.16.2004, page 6 of 6 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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